CMPEN 270: Digital Design: Theory and Practice

Textbook Information

  • Textbook: David M. Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Ed. Morgan Kauffman, 2012. ISBN-13: 978-0-12-394424-5
    • An eBook version of the 1st edition is available from the Penn State library (for free) that is nearly identical to the 2nd edition for the sections used in this course.

Published Remarks

  • None

Hardware Requirements

Software Requirements

  • Software: Vivado HL WebPACK Edition (https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
    • WebPACK is a free version

Proctored Exams

  • None

Course Description

Introduction to digital systems and their design.  Topics include combinational and sequential devices and circuits, modern design tools, and design practices.

Prerequisite:  PHYS 212

Course Overview:

CMPEN 270 Digital Design: Theory and Practice (4)  CMPEN 270 is a first course in digital systems and digital system’s design. It lays the groundwork for many later courses in computer organization and architecture and switching theory. The course includes both a lecture component to introduce important concepts, principles, methodologies and theories and a laboratory component in which the lecture material can be applied and practiced. The course introduces the theoretical foundation for digital systems including number systems, a variety of commonly used codes and Boolean algebra. Combinational devices, logic gates, and sequential devices, latches and flip-flops are introduced along with design techniques, methods and tools. Design criteria and objectives are considered and design trade-offs are examined. Higher level design elements are also examined such as decoders, multiplexers, counters, and registers, and their use in system design. Students are exposed to a variety of design tools and implementation techniques, including schematic capture tools, simulation tools, Hardware Description Languages (HDL) and HDL design tools. Laboratory work includes the design, construction and debugging of a variety of digital circuits, and the use of standard laboratory tools such as the oscilloscope and logic analyzer, and various software design tools.

Course Outline:

Module 1 – Digital Abstraction, Number Systems Module 2 – Logic Gates, Introduction to Combinational Logic Circuits Module 3 – Boolean Equations, Boolean Algebra Module 4 – From Logic to Gates Module 5 – Karnaugh Maps, Timing Module 6 – Combinational Building Blocks Module 7 – Introduction to Sequential Logic Circuits Module 8 –  Synchronous Logic Design, Adders and Counters Module 9 –  Introduction to Finite State Machines (FSMs) Module 10 – Moore and Mealy Machines, Factoring FSMs Module 11 – Timing of Sequential Logic, Synchronizers Module 12 – Subtraction, Arithmetic and Logic Unit (ALU) Module 13 – Memory Module 14 – Fixed-Point and Floating-Point Number Systems Module 15 – Putting it All Together (Guided Project)

Learning Goals

Upon successful completion of this course, students will be able to:

  • Convert signed and unsigned integers between decimal, binary and hexadecimal formats
  • Manually perform operations on binary numbers including addition, subtraction, rotate and shift
  • Compare and contrast fixed-point and floating-point numbers and convert between them and decimal formats
  • Convert between a truth table, Boolean expression, digital circuit and a textual description of a logic function
  • Express a given logic function in SOP or POS canonical form, with and without don’t cares
  • Compare and contrast synchronous logic with asynchronous logic
  • Compare and contrast memory elements including registers, register files, RAM and ROM
  • Design a finite state machine that meets a given specification
  • Design a circuit using datapath and control to meet a given specification
  • Use VHDL to formally describe a digital circuit and implement it in an FPGA
  • Create effective tests to verify proper operation of a digital circuit

Outcomes

Upon completion of the course, students should be able to:

  • Describe how numbers are stored and manipulated in computer hardware
  • Manipulate and simplify logic functions, and implement them as a digital circuit
  • Describe the advantages and disadvantages of synchronous and asynchronous circuits
  • Describe the advantages and disadvantages of different memory elements
  • Design finite state machines
  • Design datapath and control circuits
  • Implement digital circuits in an FPGA and design tests to verify their proper operation

This course supports the following ABET outcomes:

  ABET outcomes Relevancy
(a) an ability to apply knowledge of mathematics, science, and engineering Students use discrete mathematics to design digital circuits
(e) an ability to identify, formulate, and solve engineering problems Students design, implement and test digital circuits to meet engineering specifications
(k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice Students use Xilinx Vivado to design, implement, and test digital circuits

Course Requirements and Grading

Your grade for the course will be determined by the following grading scale:

Percentage Letter Grade
93 – 100 A
90 – 92.9 A-
87 – 89.9 B+
83 – 86.9 B
80 – 82.9 B-
77 – 79.9 C+
72 – 76.9 C
65 – 71.9 D
> 64.9 F

Your final grade is calculated based on the following components:

Assignment Percent
Homework 15%
Quizzes 30%
Labs 35%
Final Exam 20%
Total 100%

If you have a question about any graded material (homework, quiz, lab, etc.) discuss it with the instructor as soon as possible.  Grades are final one week after the material is returned. Homework: Each module includes a homework assignment that reinforces the material covered in the lessons for the week.  Each homework assignment is given a point value.  Your overall homework grade for the course is the total number of points earned on all homework assignments divided by the total point value of all homework assignments. Quizzes: There is a quiz in each module.  Each quiz focuses on the material in that module, but often requires knowledge gained in previous modules.  Each quiz is given a point value.  Your overall quiz grade for the course is the total number of points earned on all quizzes assignments divided by the total point value of all quizzes. Labs: Each module includes a lab assignment that reinforces material covered in the lessons and often introduces new material as well.  Each lab assignment assignment is given a point value.  Your overall lab grade for the course is the total number of points earned on all lab assignments divided by the total point value of all lab assignments. Some labs will be done individually and some labs will be done by teams of two or three students.  Lab teams will be assigned by the instructor and will change each week. Final Exam: There is a final exam at the end of the course.  The final exam is comprehensive. General:

  • Labs and homework are expected to be clear, neat, and legible.  Work that is sloppy or illegible may have points deducted or be rejected.
  • All graded work must be submitted by the due date and time.  Late work is not accepted, unless an extension is granted for a valid reason in advance (or as soon as possible in the event of an emergency). In the unusual event that late work is accepted, the grade will be reduced as follows:
    • Less than 24 hours late:  Grade reduced by 10% of assignment value
    • 24 hours to less than 1 week late:  Grade reduced by 30% of assignment value
    • 1 week to less than 2 weeks late:  Grade reduced by 50% of assignment value
    • 2 weeks or more late:  Grade reduced by 99% of assignment value
  • Lab reports and homework will not be graded without a signed acknowledgement statement that reads “This work is entirely my own and I did not provide any assistance except as noted,” followed by your signature. Acknowledge any assistance you receive, such as “Jane Doe helped me find errors in my VHDL source file file for problem (4) so it would simulate properly.”  Acknowledge any assistance you provide, such as “I helped John Doe find errors in his VHDL source file for problem (4) so it would simulate properly.”
  • Students are encouraged to help each other understand the material in this class.  However, all graded assignments must be completed independently to receive full credit, unless specified otherwise in the assignment.  Copying work is not acceptable.  Any assistance received or given must be properly acknowledged as noted above.  Failure to do so may be a violation of the academic integrity policy.